 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC2444/ltc2445/ ltc2448/ltc2449 1 sn2444589 2444589fs features descriptio u applicatio s u typical applicatio u high speed multiplexing weight scales auto ranging 6-digit dvms direct temperature measurement high speed data acquisition up to 8 differential or 16 single-ended input channels up to 8khz output rate up to 4khz multiplexing rate selectable speed/resolution 2 v rms noise at 1.76khz output rate 200nv rms noise at 13.8hz output rate with simultaneous 50/60hz rejection guaranteed modulator stability and lock-up immunity for any input and reference conditions 0.0005% inl, no missing codes autosleep enables 20 a operation at 6.9hz <5 v offset (4.5v < v cc < 5.5v, 40 c to 85 c) differential input and differential reference with gnd to v cc common mode range no latency mode, each conversion is accurate even after a new channel is selected internal oscillatorno external components ltc2445/ltc2449 include muxout/adcin for external buffering or gain tiny qfn 5mm x 7mm package 24-bit high speed 8-/16-channel ? adcs with selectable speed/resolution the ltc ? 2444/ltc2445/ltc2448/ltc2449 are 8-/16- channel (4-/8-differential) high speed 24-bit no latency ? tm adcs. they use a proprietary delta-sigma architec- ture enabling variable speed/resolution. through a simple 4-wire serial interface, ten speed/resolution combinations 6.9hz/280nv rms to 3.5khz/25 v rms (4khz with external oscillator) can be selected with no latency between con- version results or shift in dc accuracy (offset, full-scale, linearity, drift). additionally, a 2x speed mode can be selected enabling output rates up to 7khz (8khz if an external oscillator is used) with one cycle latency. any combination of single-ended or differential inputs can be selected with a common mode input range from ground to v cc , independent of v ref . while operating in the 1x speed mode the first conversion following a new speed, resolution, or channel selection is valid. since there is no settling time between conversions, all 8 differential chan- nels can be scanned at a rate of 500hz. at the conclusion of each conversion, the converter is internally reset elimi- nating any memory effects between successive conver- sions and assuring stability of the high order delta-sigma modulator. , ltc and lt are registered trademarks of linear technology corporation. LTC2444/ltc2448 speed vs rms noise simple 24-bit variable speed data acquisition system sdi sck sdo cs f o ref + v cc 4.5v to 5.5v 1 f com ref C gnd thermocouple variable speed/ resolution differential 24-bit ? adc 16-channel mux + C 2444 ta01 4-wire spi interface ltc2448 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate) ch0 ch1 ? ? ? ? ? ? ch7 ch8 ch15 conversion rate (hz) 1 0.1 rms noise ( v) 1 10 100 10 100 2440 ta02 1000 10000 2.8 v at 880hz 280nv at 6.9hz (50/60hz rejection) v cc = 5v v ref = 5v v in + = v in C = 0v 2x speed mode no latency mode no latency ? is a trademark of linear technology corporation.
LTC2444/ltc2445/ ltc2448/ltc2449 2 sn2444589 2444589fs order part number order part number absolute axi u rati gs w ww u package/order i for atio uu w (notes 1, 2) supply voltage (v cc ) to gnd .......................C 0.3v to 6v analog input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) reference input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) t jmax = 125 c, ja = 34 c/w LTC2444cuhf LTC2444iuhf qfn part marking* 2444 operating temperature range LTC2444c/ltc2445c/ ltc2448c/ltc2449c .............................. 0 c to 70 c LTC2444i/ltc2445i/ ltc2448i/ltc2449i ........................... C 40 c to 85 c storage temperature range ................. C 65 c to 125 c ltc2448cuhf ltc2448iuhf qfn part marking* 2448 13 14 15 16 top view uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd busy ext gnd gnd gnd com nc ch0 ch1 nc nc gnd ref C ref + v cc nc nc nc nc nc ch7 ch6 nc sck sdo cs f o sdi gnd gnd ch2 ch3 nc nc ch4 ch5 nc 23 22 21 20 9 10 11 12 13 14 15 16 top view uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd busy ext gnd gnd gnd com ch0 ch1 ch2 ch3 ch4 gnd ref C ref + v cc nc nc nc nc ch15 ch14 ch13 ch12 sck sdo cs f o sdi gnd gnd ch5 ch6 ch7 ch8 ch9 ch10 ch11 23 22 21 20 9 10 11 12 t jmax = 125 c, ja = 34 c/w order part number order part number t jmax = 125 c, ja = 34 c/w ltc2445cuhf ltc2445iuhf qfn part marking* 2445 *the temperature grade is identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. ltc2449cuhf ltc2449iuhf qfn part marking* 2449 t jmax = 125 c, ja = 34 c/w 13 14 15 16 top view uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd busy ext gnd gnd gnd com nc ch0 ch1 nc nc gnd ref C ref + v cc muxoutn adcinn adcinp muxoutp nc ch7 ch6 nc sck sdo cs f o sdi gnd gnd ch2 ch3 nc nc ch4 ch5 nc 23 22 21 20 9 10 11 12 13 14 15 16 top view uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd busy ext gnd gnd gnd com ch0 ch1 ch2 ch3 ch4 gnd ref C ref + v cc muxoutn adcinn adcinp muxoutp ch15 ch14 ch13 ch12 sck sdo cs f o sdi gnd gnd ch5 ch6 ch7 ch8 ch9 ch10 ch11 23 22 21 20 9 10 11 12 LTC2444/ltc2445/ ltc2448/ltc2449 3 sn2444589 2444589fs electrical characteristics parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) 24 bits integral nonlinearity v cc = 5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) 5 15 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 3 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, 2.5 5 v gnd in + = in C v cc (note 12) offset error drift 2.5v ref + v cc , ref C = gnd, 20 nv/ c gnd in + = in C v cc positive full-scale error ref + = 5v, ref C = gnd, in + = 3.75v, in C = 1.25v 10 50 ppm of v ref ref + = 2.5v, ref C = gnd, in + = 1.875v, in C = 0.625v 10 50 ppm of v ref positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.2 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative full-scale error ref + = 5v, ref C = gnd, in + = 1.25v, in C = 3.75v 10 50 ppm of v ref ref + = 2.5v, ref C = gnd, in + = 0.625v, in C = 1.875v 10 50 ppm of v ref negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.2 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 15 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 15 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 15 ppm of v ref input common mode rejection dc 2.5v ref + v cc , ref C = gnd, 120 db gnd in C = in + v cc the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) symbol parameter conditions min typ max units in + absolute/common mode in + voltage gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage gnd C 0.3v v cc + 0.3v v v in input differential voltage range Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage 0.1 v cc v ref C absolute/common mode ref C voltage gnd v cc C 0.1v v v ref reference differential voltage range 0.1 v cc v (ref + C ref C ) c s(in+) in + sampling capacitance 2 pf c s(inC) in C sampling capacitance 2 pf c s(ref+) ref + sampling capacitance 2 pf c s(refC) ref C sampling capacitance 2 pf i dc_leak(in+, inC, leakage current, inputs and reference cs = v cc , in + = gnd, in C = gnd, C15 1 15 na ref+, refC) ref + = 5v, ref C = gnd i sample(in+, inC, average input/reference current varies, see applications section na ref+, refC) during sampling t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a u d refere ce uu u LTC2444/ltc2445/ ltc2448/ltc2449 4 sn2444589 2444589fs ti i g characteristics u w symbol parameter conditions min typ max units v cc supply voltage 4.5 5.5 v i cc supply current conversion mode cs = 0v (note 7) 811 ma sleep mode cs = v cc (note 7) 830 a the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) power require e ts w u the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 4.5v v cc 5.5v 2.5 v cs, f o v il low level input voltage 4.5v v cc 5.5v 0.8 v cs, f o v ih high level input voltage 4.5v v cc 5.5v (note 8) 2.5 v sck v il low level input voltage 4.5v v cc 5.5v (note 8) 0.8 v sck i in digital input current 0v v in v cc C10 10 a cs, f o , ext, soi i in digital input current 0v v in v cc (note 8) C10 10 a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 8) 10 pf sck v oh high level output voltage i o = C800 a v cc C 0.5v v sdo, busy v ol low level output voltage i o = 1.6ma 0.4v v sdo, busy v oh high level output voltage i o = C800 a (note 9) v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 9) 0.4v v sck i oz hi-z output leakage C10 10 a sdo digital i puts a d digital outputs uu the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units f eosc external oscillator frequency range 0.1 20 mhz t heo external oscillator high period 25 10000 ns t leo external oscillator low period 25 10000 ns t conv conversion time osr = 256 (sdi = 0) 0.99 1.13 1.33 ms osr = 32768 (sdi = 1) 126 145 170 ms external oscillator (notes 10, 13) 40 ? osr +170 f eosc (khz) ms f isck internal sck frequency internal oscillator (note 9) 0.8 0.9 1 mhz external oscillator (notes 9, 10) f eosc /10 hz LTC2444/ltc2445/ ltc2448/ltc2449 5 sn2444589 2444589fs symbol parameter conditions min typ max units d isck internal sck duty cycle (note 9) 45 55 % f esck external sck frequency range (note 8) 20 mhz t lesck external sck low period (note 8) 25 ns t hesck external sck high period (note 8) 25 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 9, 11) 41.6 35.3 30.9 s external oscillator (notes 9, 10) 320/f eosc s t dout_esck external sck 32-bit data output time (note 8) 32/f esck s t 1 cs to sdo low z (note 12) 025ns t 2 cs to sdo high z (note 12) 025ns t 3 cs to sck (note 9) 5 s t 4 cs to sck (notes 8, 12) 25 ns t kqmax sck to sdo valid 25 ns t kqmin sdo hold after sck (note 5) 15 ns t 5 sck set-up before cs 50 ns t 6 sck hold after cs 50 ns t 7 sdi setup before sck (note 5) 10 ns t 8 sdi hold after sck (note 5) 10 ns the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics w u gnd (pins 1, 4, 5, 6, 31, 32, 33): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a common ground plane through a low impedance connection. all 7 pins must be connected to ground for proper operation. busy (pin 2): conversion in progress indicator. this pin is high while the conversion is in progress and goes low indicating the conversion is complete and data is ready. it remains low during the sleep and data output states. at the conclusion of the data output state, it goes high indicating a new conversion has begun. ext (pin 3): internal/external sck selection pin. this pin is used to select internal or external sck for outputting/ inputting data. if ext is tied low, the device is in the external sck mode and data is shifted out of the device under the control of a user applied serial clock. if ext is tied high, the internal serial clock mode is selected. the device generates its own sck signal and outputs this on the sck pin. a framing signal busy (pin 2) goes low indicating data is being output. com (pin 7): the common negative input (in C ) for all single ended multiplexer configurations. the voltage on ch0-ch15 and com pins can have any value between uu u pi fu ctio s note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 4.5v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to external conversion clock source with f eosc = 10mhz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: the converter uses the internal oscillator. note 8: the converter is in external sck mode of operation such that the sck pin is used as a digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in hz. note 9: the converter is in internal sck mode of operation such that the sck pin is used as a digital output. in this mode of operation, the sck pin has a total equivalent load capacitance of c load = 20pf. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in hz. note 11: the converter uses the internal oscillator. f o = 0v. note 12: guaranteed by design and test correlation. note 13: there is an internal reset that adds an additional 1 s (typ) to the conversion time. LTC2444/ltc2445/ ltc2448/ltc2449 6 sn2444589 2444589fs default mode of operation is ch0-ch1, osr of 256, and 1x mode. the serial data input contains an enable bit which determines if a new channel/speed is selected. if this bit is low the following conversion remains at the same speed and selected channel. the serial data input is applied to the device under control of the serial clock (sck) during the data output cycle. the first conversion following a new channel/speed is valid. f o (pin 35): frequency control pin. digital input that controls the internal conversion clock. when f o is con- nected to v cc or gnd, the converter uses its internal oscillator running at 9mhz. the conversion rate is deter- mined by the selected osr such that t conv (ms) = 40 ? osr + 170/f osc (khz). the first digital filter null is located at 8/t conv , 7khz at osr = 256 and 55hz (simultaneous 50/ 60hz) at osr = 32768. this pin may be driven with a maximum external clock of 10.24mhz resulting in a maxi- mum 8khz output rate (osr = 64, 2x mode). cs (pin 36): active low chip select. a low on this pin enables the sdo ditital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output aborts the data transfer and starts a new conversion. sdo (pin 37): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. this signal is high while the conversion is in progress and goes low once the conversion is complete. sck (pin 38): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as a digital output for the internal serial interface clock during the data output period. in the external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. the serial clock operation mode is determined by the logic level applied to the ext pin. gnd C 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and under-range output codes. ch0 to ch15 (pins 8-23): ltc2448/ltc2449 analog inputs. may be programmed for single-ended or differen- tial mode. ch0 to ch7 (pins 9, 10, 13, 14, 17, 18, 21, 22): LTC2444/ ltc2445 analog inputs. may be programmed for single- ended or differential mode. nc (pins 8, 11, 12, 15, 16, 19, 20, 23): LTC2444/ ltc2445 no connect/channel isolation shield. may be left floating or tied to any voltage 0 to v cc in order to provide isolation for pairs of differential input channels. nc (pins 24, 25, 26, 27): LTC2444/ltc2448 no connect. these pins can either be tied to ground or left floating. muxoutp (pin 24): ltc2445/ltc2449 positive multi- plexer output. used to drive the input to an external buffer/ amplifier. adcinp (pin 25): ltc2445/ltc2449 positive adc input. tie to output of buffer/amplifier driven by muxoutp. adcinn (pin 26): ltc2445/ltc2449 negative adc input. tie to output of buffer/amplifier driven by muxoutn. muxoutn (pin 27): ltc2445/ltc2449 negative multi- plexer output. used to drive the input to an external buffer/ amplifier. v cc (pin 28): positive supply voltage. bypass to gnd with a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor as close to the part as possible. ref + (pin 29), ref (pin 30): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the negative reference input, ref + , by at least 0.1v. sdi (pin 34): serial data input. this pin is used to select the speed, 1x or 2x mode, resolution, and input channel, for the next conversion cycle. at initial power up, the pi fu ctio s uuu LTC2444/ltc2445/ ltc2448/ltc2449 7 sn2444589 2444589fs test circuits fu ctio al block diagra uu w figure 1. functional block diagram 1.69k sdo 2440 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2440 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc applicatio s i for atio wu u u converter operation converter operation cycle the LTC2444/ltc2445/ltc2448/ltc2449 are multi- channel, high speed, delta-sigma analog-to-digital con- verters with an easy to use 3- or 4-wire serial interface (see figure 1). their operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output/input (see figure 2). the 4-wire interface consists of serial data input (sdi), serial data output (sdo), serial clock (sck) and chip select (cs). the inter- face, timing, operation cycle and data out format is com- patible with linears entire family of ? converters. figure 2. LTC2444/ltc2445/ltc2448/ltc2449 state transition diagram autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator serial interface gnd v cc ch0 ch1 ? ? ? ch15 com in + in C mux sdo sck ref + ref C cs sdi f o (int/ext) 2444 f01 + C convert sleep channel select speed select data output power up in + =ch0, in C =ch1 osr=256,1x mode 2444 f02 cs = low and sck LTC2444/ltc2445/ ltc2448/ltc2449 8 sn2444589 2444589fs initially, the LTC2444/ltc2445/ltc2448/ltc2449 per- form a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced below 10 a. the part remains in the sleep state as long as cs is high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result while operating in the 1x mode. the data output cor- responds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the con- trol of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs, sck and ext pins, the LTC2444/ltc2445/ltc2448/ltc2449 offer several flex- ible modes of operation (internal or external sck). these various modes do not require programming configuration registers; moreover, they do not disturb the cyclic opera- tion described above. these modes of operation are described in detail in the serial interface timing modes section. ease of use the LTC2444/ltc2445/ltc2448/ltc2449 data output has no latency, filter settling delay or redundant data associated with the conversion cycle while operating in the 1x mode. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. speed/ resolution adjustments may be made seamlessly be- tween two conversions without settling errors. the LTC2444/ltc2445/ltc2448/ltc2449 perform off- set and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. applicatio s i for atio wu u u power-up sequence the LTC2444/ltc2445/ltc2448/ltc2449 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2.2v. this fea- ture guarantees the integrity of the conversion result and of the serial interface mode selection. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. the conversion imme- diately following a por is performed on the input channel in + = ch0, in C = ch1 at an osr = 256 in the 1x mode. following the por signal, the LTC2444/ltc2445/ltc2448/ ltc2449 start a normal conversion cycle and follow the succession of states described above. the first conver- sion result following por is accurate within the specifica- tions of the device if the power supply voltage is restored within the operating range (4.5v to 5.5v) before the end of the por time interval. reference voltage range these converters accept a truly differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the LTC2444/ltc2445/ltc2448/ltc2449 can accept a differential reference voltage from 0.1v to v cc . the con- verter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the converters overall inl performance. input voltage range the analog input is truly differential with an absolute/ common mode range for the ch0-ch15 and com input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the LTC2444/ltc2445/ LTC2444/ltc2445/ ltc2448/ltc2449 9 sn2444589 2444589fs ltc2448/ltc2449 convert the bipolar differential input signal, v in = in + C in C (where in + and in C are the selected input channels), from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the con- verter indicates the overrange or the underrange condition using distinct output codes. muxout/adcin there are two differences between the LTC2444/ltc2448 and the ltc2445/ltc2449. the first is the rms noise performance. for a given osr, the ltc2445/ltc2449 noise level is approximately 2 times lower (0.5 effective bits)than that of the LTC2444/ltc2448. the second difference is the ltc2445/ltc2449 includes muxout/adcin pins. these pins enable an external buffer or gain block to be inserted between the output of the multiplexer and the input to the adc. since the buffer is driven by the output of the multiplexer, only one circuit is required for all 16 input channels. additionally, the trans- parent calibration feature of the ltc244x family automati- cally removes the offset errors of the external buffer. in order to achieve optimum performance, the muxout and adcin pins should not be shorted together. in appli- cations where the muxout and adcin need to be shorted together, the LTC2444/ltc2448 should be used because the muxout and adcin are internally connected for optimum performance. output data format the LTC2444/ltc2445/ltc2448/ltc2449 serial output data stream is 32 bits long. the first 3 bits represent status information indicating the sign and conversion state. the next 24 bits are the conversion result, msb first. the remaining 5 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. in the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible (see table 5). under these conditions, sub lsbs are included in the conversion result and represent useful information beyond the 24-bit level. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. LTC2444/ltc2445/ltc2448/ltc2449 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig msb v in 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 28-5 are the 24-bit conversion result msb first. bit 5 is the least significant bit (lsb). bits 4-0 are sub lsbs below the 24-bit level. bits 4-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and sck is ignored. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the applicatio s i for atio wu u u LTC2444/ltc2445/ ltc2448/ltc2449 10 sn2444589 2444589fs serial interface pins the LTC2444/ltc2445/ltc2448/ltc2449 transmit the conversion results and receive the start of conversion command through a synchronous 3- or 4-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed, resolution and input channel. serial clock input/output (sck) the serial clock signal present on sck (pin 38) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the LTC2444/ltc2445/ltc2448/ltc2449 cre- ate their own serial clock. in the external sck mode of operation, the sck pin is used as input. the internal or first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. table 2. LTC2444/ltc2445/ltc2448/ltc2449 output data format differential input voltage bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 0 v in * eoc dmy sig msb v in * 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . applicatio s i for atio wu u u msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 2444 f04 sig bit 29 0 bit 30 eoc hi-z cs sck sdi sdo busy bit 31 1 0 en sgl a2 a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 figure 3. sdi speed/resolution, channel selection, and data output timing LTC2444/ltc2445/ ltc2448/ltc2449 11 sn2444589 2444589fs external sck mode is selected by tying ext (pin 3) low for external sck and high for internal sck. serial data output (sdo) the serial data output pin, sdo (pin 37), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 36) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 36), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the LTC2444/ltc2445/ltc2448/ ltc2449 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state. serial data input (sdi) the serial data input (sdi, pin 34) is used to select the speed/resolution and input channel of the LTC2444/ ltc2445/ltc2448/ltc2449. sdi is programmed by a serial input data stream under the control of sck during the data output cycle, see figure 3. initially, after powering up, the device performs a conver- sion with in + = ch0, in C = ch1, osr = 256 (output rate nominally 880hz), and 1x speedup mode (no latency). once this first conversion is complete, the device enters the sleep state and is ready to output the conversion result and receive the serial data input stream programming the speed/resolution and input channel for the next conver- sion. at the conclusion of each conversion cycle, the device enters this state. in order to change the speed/resolution or input channel, the first 3 bits shifted into the device are 101. this is compatible with the programming sequence of the ltc2414/ltc2418. if the sequence is set to 000 or 100, the following input data is ignored (dont care) and the previously selected speed/resolution and channel remain valid for the next conversion. combinations other than 101, 100, and 000 of the 3 control bits should be avoided. if the first 3 bits shifted into the device are 101, then the following 5 bits select the input channel for the following conversion (see tables 3 and 4). the next 5 bits select the speed/resolution and mode 1x (no latency) 2x (double output rate with one conversion latency), see table 5. if these 5 bits are set to all 0s, the previous speed remains selected for the next conversion. this is useful in applica- tions requiring a fixed output rate/resolution but need to change the input channel. in this case, the timing and input sequence is compatible with the ltc2414/ltc2418. when an update operation is initiated (the first 3 bits are 101) the first 5 bits are the channel address. the first bit, sgl, determines if the input selection is differential (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input. for sgl = 1, one of 8 channels (LTC2444/ltc2445) or one of 16 channels (ltc2448/ltc2449) is selected as the positive input. the negative input is com for all single ended operations. the remaining 4 bits (odd, a2, a1, a0) determine which channel is selected. the ltc2448/ ltc2449 use all 4 bits to select one of 16 different input channels (see table 3) while in the case of the LTC2444/ ltc2445, a2 is always 0, and the remaining 3 bits select one of 8 different input channels (see table 4). applicatio s i for atio wu uu LTC2444/ltc2445/ ltc2448/ltc2449 12 sn2444589 2444589fs table 3. channel selection for the ltc2448/ltc2449 mux address channel selection odd/ sgl sign a2 a1 a0 0 123456789101112131415com *00000in + in C 00001 in + in C 00010 in + in C 00011 in + in C 00100 in + in C 00101 in + in C 00110 in + in C 00111 in + in C 01000in C in + 01001 in C in + 01010 in C in + 01011 in C in + 01100 in C in + 01101 in C in + 01110 in C in + 01111 in C in + 10000in + in C 10001 in + in C 10010 in + in C 10011 in + in C 10100 in + in C 10101 in + in C 10110 in + in C 10111 in + in C 11000 in + in C 11001 in + in C 11010 in + in C 11011 in + in C 11100 in + in C 11101 in + in C 11110 in + in C 11111 in + in C *default at power up applicatio s i for atio wu u u LTC2444/ltc2445/ ltc2448/ltc2449 13 sn2444589 2444589fs applicatio s i for atio wu u u table 4. channel selection for the LTC2444/ltc2445 (bit a2 should always be 0) mux address channel selection odd/ sgl sign a2 a1 a0 01234567com *0 0 000 in + in C 0 0 001 in + in C 0 0 010 in + in C 0 0 011 in + in C 0 1 000 in C in + 0 1 001 in C in + 0 1 010 in C in + 0 1 011 in C in + 1 0 000 in + in C 1 0 001 in + in C 1 0 010 in + in C 1 0 011 in + in C 1 1 000 in + in C 1 1 001 in + in C 1 1 010 in + in C 1 1 011 in + in C *default at power up LTC2444/ltc2445/ ltc2448/ltc2449 14 sn2444589 2444589fs table 5. LTC2444/ltc2445/ltc2448/ltc2449 speed/resolution selection conversion rate rms rms osr3 osr2 osr1 osr0 twox internal external noise noise enob enob osr latency 9mhz 10.24mhz LTC2444/ ltc2445/ LTC2444/ ltc2445/ clock clock ltc2448 ltc2449 ltc2448 ltc2449 00000 k eep previous speed/resolution 000103. 52khz 4khz 23 v23 v 17 17 64 none 001001. 76khz 2khz 4.4 v 3.5 v 20.1 20.1 128 none 00110 880hz 1khz 2.8 v2 v 20.8 21.3 256 none 01000 440hz 500hz 2 v 1.4 v 21.3 21.8 512 none 01010 220hz 250hz 1.4 v1 v 21.8 22.4 1024 none 01100 110hz 125hz 1.1 v 750nv 22.1 22.9 2048 none 01110 55hz 62.5hz 720nv 510nv 22.7 23.4 4096 none 10000 27.5hz 31.25hz 530nv 375nv 23.2 24 8192 none 1001013. 75hz 15.625hz 350nv 250nv 23.8 24.4 16384 none 111106. 875hz 7.8125hz 280nv 200nv 24.1 24.6 32768 none 00001 k eep previous speed/resolution 000117. 04khz 8khz 23 v23 v 17 17 64 1 cycle 001013. 52khz 4khz 4.4 v 3.5 v 20.1 20.1 128 1 cycle 001111. 76khz 2khz 2.8 v2 v 20.8 21.3 256 1 cycle 01001 880hz 1khz 2 v 1.4 v 21.3 21.8 512 1 cycle 01011 440hz 500hz 1.4 v1 v 21.8 22.4 1024 1 cycle 01101 220hz 250hz 1.1 v 750nv 22.1 22.9 2048 1 cycle 01111 110hz 125hz 720nv 510nv 22.7 23.4 4096 1 cycle 10001 55hz 62.5hz 530nv 375nv 23.2 24 8192 1 cycle 10011 27.5hz 31.25hz 350nv 250nv 23.8 24.4 16384 1 cycle 1111113. 75hz 15.625hz 280nv 200nv 24.1 24.6 32768 1 cycle applicatio s i for atio wu uu LTC2444/ltc2445/ ltc2448/ltc2449 15 sn2444589 2444589fs speed multiplier mode in addition to selecting the speed/resolution, a speed multiplier mode is used to double the output rate while maintaining the selected resolution. the last bit of the 5-bit speed/resolution control word (twox, see table 5) deter- mines if the output rate is 1x (no speed increase) or 2x (double the selected speed). while operating in the 1x mode, the device combines two internal conversions for each conversion result in order to remove the adc offset. every conversion cycle, the offset and offset drift are transparently calibrated greatly simpli- fying the user interface. the resulting conversion result has no latency. the first conversion following a newly selected speed/resolution and input channel is valid. this is identical to the operation of the ltc2440, ltc2414 and ltc2418. while operating in the 2x mode, the device performs a running average of the last two conversion results. this automatically removes the offset and drift of the device while increasing the output rate by 2x. the resolution (noise) remains the same. if a new channel is selected, the conversion result is valid for all conversions after the first conversion (one cycle latency). if a new speed/resolution is selected, the first conversion result is valid but the resolution (noise) is a function of the running average. all subsequent conversion results are valid. if the mode is changed from either 1x to 2x or 2x to 1x without changing the resolution or channel, the first conversion result is valid. if an external buffer/amplifier circuit is used for the ltc2445/ltc2449, the 2x mode can be used to increase the settling time of the amplifier between readings. while operating in the 2x mode, the multiplexer output (input to the external buffer/amplifier) is switched at the end of each conversion cycle. prior to concluding the data out/in cycle, the analog multiplexer output is switched. this occurs at the end of the conversion cycle (just prior to the data output cycle) for auto calibration. the time required to read the conversion enables more settling time for the external buffer/amplifier. the offset/offset drift of the external amplifier is automatically removed by the converters auto calibration sequence for both the 1x and 2x speed modes. while operating in the 1x mode, if a new input channel is selected the multiplexer is switched on the falling edge of the 14th sck (once the complete data input word is programmed). the remaining data output sequence time can be used to allow the external buffer/amplifier to settle. busy the busy output (pin 2) is used to monitor the state of conversion, data output and sleep cycle. while the part is converting, the busy pin is high. once the conversion is complete, busy goes low indicating the conversion is complete and data out is ready. the part now enters the low power sleep state. busy remains low while data is shifted out of the device and sdi is shifted into the device. it goes high at the conclusion of the data input/output cycle indicating a new conversion has begun. this rising edge may be used to flag the completion of the data read cycle. serial interface timing modes the LTC2444/ltc2445/ltc2448/ltc2449s 3- or 4-wire interface is spi and microwire compatible. this inter- face offers several flexible modes of operation. these in- clude internal/external serial clock, 3- or 4-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. refer to table 6 for a summary. table 6. LTC2444/ltc2445/ltc2448/ltc2449 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 4, 5 external sck, 2-wire i/o external sck sck figure 6 internal sck, single cycle conversion internal cs cs figures 7, 8 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 9 applicatio s i for atio wu uu LTC2444/ltc2445/ ltc2448/ltc2449 16 sn2444589 2444589fs external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 4. the serial clock mode is selected by the ext pin. to select the external serial clock mode, ext must be tied low. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 (busy = 1) while a conversion is in progress and eoc = 0 (busy = 0) if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. the device remains in the sleep state until the first rising edge of sck is seen. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) and busy goes high indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z and busy monitored for the completion of a conversion. figure 4. external serial clock, single cycle operation msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 2444 f05 sig bit 29 0 bit 30 eoc hi-z cs sck (external) sdi sdo busy bit 31 1 0 en sgl a2 a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 conversion sleep data output conversion test eoc test eoc v cc f o ref + ref C ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 15 16 23 7 38 37 1,4,5,6,31,32,33 36 34 reference voltage 0.1v to v cc analog inputs 2 = external oscillator = internal oscillator 1 f 2.7v to 5.5v ltc2448 4-wire spi interface ? ? ? ? ? ? ? ? ? ? ? ? busy applicatio s i for atio wu uu LTC2444/ltc2445/ ltc2448/ltc2449 17 sn2444589 2444589fs as described above, cs may be pulled low at any time in order to monitor the conversion status on the sdo pin. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the fifth falling edge and the 32nd falling edge of sck, see figure 5. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. thirteen serial input data bits are required in order to properly program the speed/resolution and input channel. if the data output applicatio s i for atio wu u u figure 5. external serial clock, reduced output data length cs sck (external) sdi sdo busy 123456 15 msb bit 28 bit 27 bit 26 bit 25 sig bit 29 0 bit 30 eoc hi-z hi-z bit 31 2444 f06 conversion sleep sleep data output data output conversion conversion test eoc don't care don't care v cc f o ref + ref C ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 15 16 23 7 38 37 1,4,5,6,31,32,33 36 34 reference voltage 0.1v to v cc analog inputs 2 = external oscillator = internal oscillator 1 f 2.7v to 5.5v ltc2448 4-wire spi interface ? ? ? ? ? ? ? ? ? ? ? ? busy don't care sequence is aborted prior to the 13th rising edge of sck, the new input data is ignored, and the previously selected speed/resolution and channel are used for the next con- version cycle. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. if a new channel is being programmed, the rising edge of cs must come after the 14th falling edge of sck in order to store the data input sequence. LTC2444/ltc2445/ ltc2448/ltc2449 18 sn2444589 2444589fs applicatio s i for atio wu u u external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 6. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected by tying ext low. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. conversely, busy (pin 2) may be used to monitor the status of the conversion cycle. eoc or busy may be used as an interrupt to an external controller cs sck (external) sdi sdo busy 2444 f07 conversion sleep data output conversion msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb sig bit 29 0 bit 30 eoc bit 31 1 0 en sgl a2 a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 don't care don't care v cc f o ref + ref C ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 15 16 23 7 38 37 1,4,5,6,31,32,33 36 34 reference voltage 0.1v to v cc analog inputs 2 = external oscillator = internal oscillator 1 f 2.7v to 5.5v ltc2448 4-wire spi interface ? ? ? ? ? ? ? ? ? ? ? ? busy figure 6. external serial clock, cs = 0 operation (2-wire) indicating the conversion result is ready. eoc = 1 (busy = 1) while the conversion is in progress and eoc = 0 (busy = 0) once the conversion enters the low power sleep state. on the falling edge of eoc/busy, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo and busy go high (eoc = 1) indicating a new conversion has begun. LTC2444/ltc2445/ ltc2448/ltc2449 19 sn2444589 2444589fs internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 7. in order to select the internal serial clock timing mode, the ext pin must be tied high. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. alternatively, busy (pin 2) may be used to monitor the status of the conversion in progress. busy is high during the conver- figure 7. internal serial clock, single cycle operation msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 2444 f08 sig bit 29 0 bit 30 eoc hi-z cs sck sdi sdo busy bit 31 1 0 en sgl a2 a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 conversion sleep data output conversion test eoc test eoc don't care don't care LTC2444/ltc2445/ ltc2448/ltc2449 22 sn2444589 2444589fs differential input signal frequency (hz) 47 C140 normal mode rejection (db) C130 C120 C110 C100 51 55 59 63 2440 f12 C90 C80 49 53 57 61 figure 11. LTC2444/ltc2445/ltc2448/ltc2449 normal mode rejection (internal oscillator) differential input signal frequency (hz) 0 C60 C40 0 180 2440 f11 C80 C100 60 120 240 C120 C140 C20 normal mode rejection (db) sinc 4 envelope figure 10. LTC2444/ltc2445/ltc2448/ltc2449 normal mode rejection (internal oscillator) applicatio s i for atio wu u u table 7. osr vs notch frequency (f n ) (with internal oscillator running at 9mhz) osr notch (f n ) 64 28.16khz 128 14.08khz 256 7.04khz 512 3.52khz 1024 1.76khz 2048 880hz 4096 440hz 8192 220hz 16384 110hz 32768* 55hz *simultaneous 50/60hz rejection normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the LTC2444/ltc2445/ ltc2448/ltc2449 significantly simplify antialiasing filter requirements. the LTC2444/ltc2445/ltc2448/ltc2449s speed/reso- lution is determined by the over sample ratio (osr) of the on-chip digital filter. the osr ranges from 64 for 3.5khz output rate to 32,768 for 6.9hz (in no latency mode) output rate. the value of osr and the sample rate f s determine the filter characteristics of the device. the first null of the digital filter is at f n and multiples of f n where f n = f s /osr, see figure 10 and table 7. the rejection at the frequency f n 14% is better than 80db, see figure 11. LTC2444/ltc2445/ ltc2448/ltc2449 23 sn2444589 2444589fs clock applied to f o . combining a large osr with a reduced sample rate leads to notch frequencies f n near dc while maintaining simple antialiasing requirements. a 100khz clock applied to f o results in a null at 0.6hz plus all harmonics up to 20khz, see figure 13. this is useful in applications requiring digitalization of the dc component of a noisy input signal and eliminates the need of placing a 0.6hz filter in front of the adc. an external oscillator operating from 100khz to 20mhz can be implemented using the ltc1799 (resistor set sot-23 oscillator), see figure 16. by floating pin 4 (div) of the ltc1799, the output oscillator frequency is: f mhz k r osc set = ? ? ? ? ? ? 10 10 10 ? ? the normal mode rejection characteristic shown in figure 13 is achieved by applying the output of the ltc1799 (with r set = 100k) to the f o pin on the LTC2444/ltc2445/ ltc2448/ltc2449 with sdi tied high (osr = 32768). figure 13. LTC2444/ltc2445/ltc2448/ltc2449 normal mode rejection (external oscillator at 90khz) differential input signal frequency (hz) 0 C40 C20 0 8 2440 f14 C60 C80 246 10 C100 C120 C140 normal mode rejection (db) figure 12. LTC2444/ltc2445/ltc2448/ltc2449 normal mode rejection (internal oscillator) differential input signal frequency (hz) 0 C60 C40 0 1440 f13 C80 C100 1000000 2000000 C120 1.8mhz C140 C20 normal mode rejection (db) rejection > 120db if f o is grounded, f s is set by the on-chip oscillator at 1.8mhz 5% (over supply and temperature variations). at an osr of 32,768, the first null is at f n = 55hz and the no latency output rate is f n /8 = 6.9hz. at the maximum osr, the noise performance of the device is 280nv rms (LTC2444/ ltc2448) and 200nv rms (ltc2445/ltc2449) with better than 80db rejection of 50hz 2% and 60hz 2%. since the osr is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple. the first multiple of f s occurs at 55hz ? 32,768 = 1.8mhz, see figure 12. the first null becomes f n = 7.04khz with an osr of 256 (an output rate of 880hz) and f o grounded. while the null has shifted, the sample rate remains constant. as a result of constant modulator sampling rate, the linearity, offset and full-scale performance remains unchanged as does the first multiple of f s . the sample rate f s and null f n , may also be adjusted by driving the f o pin with an external oscillator. the sample rate is f s = f eosc /5, where f eosc is the frequency of the applicatio s i for atio wu uu LTC2444/ltc2445/ ltc2448/ltc2449 24 sn2444589 2444589fs applicatio s i for atio wu u u sleep convert sleep convert sleep 8 a 2440 f15 8ma 8 a 8ma 8 a data out data out converter state supply current cs figure 14. reduced power timing mode v ref + v in + v cc r sw (typ) 500 ? i leak i leak v cc i leak i leak v cc r sw (typ) 500 ? c eq 5pf (typ) (c eq = 2pf sample cap + parasitics) r sw (typ) 500 ? i leak i in + v in C i in C i ref + i ref C 2440 f16 i leak v cc i leak i leak switching frequency f sw = 1.8mhz internal oscillator f sw = f eosc /5 external oscillator v ref C r sw (typ) 500 ? mux mux figure 15. LTC2444/ltc2448 input structure reduced power operation in addition to adjusting the speed/resolution of the LTC2444/ltc2445/ltc2448/ltc2449, the speed/reso- lution/power dissipation may also be adjusted using the automatic sleep mode. during the conversion cycle, the LTC2444/ltc2445/ltc2448/ltc2449 draw 8ma supply current independent of the programmed speed. once the conversion cycle is completed, the device automatically enters a low power sleep state drawing 8 a. the device remains in this state as long as cs is high and data is not shifted out. by adjusting the duration of the sleep state (hold cs high longer) and the duration of the conversion cycle (programming osr) the dc power dissipation can be reduced, see figure 14. average input current the LTC2444/ltc2448 switch the input and reference to a 2pf capacitor at a frequency of 1.8mhz. a simplified equivalent circuit is shown in figure 15. the sample capacitor for the ltc2445/ltc2449 is 4pf, and its aver- age input current is externally buffered from the input source. the average input and reference currents can be ex- pressed in terms of the equivalent input resistance of the sample capacitor, where: req = 1/(f sw ? ceq) when using the internal oscillator, f sw is 1.8mhz and the equivalent resistance is approximately 110k ? . LTC2444/ltc2445/ ltc2448/ltc2449 25 sn2444589 2444589fs first notch frequency this is the first notch in the sinc 4 portion of the digital filter and depends on the f o clock frequency and the oversample ratio. rejection at this frequency and its multiples (up to the modulator sample rate of 1.8mhz) exceeds 120db. this is 8 times the maximum conversion rate. effective noise bandwidth the LTC2444/ltc2445/ltc2448/ltc2449 has extremely good input noise rejection from the first notch frequency all the way out to the modulator sample rate (typically 1.8mhz). effective noise bandwidth is a measure of how the adc will reject wideband input noise up to the modu- lator sample rate. the example on the following page shows how the noise rejection of the LTC2444/ltc2445/ ltc2448/ltc2449 reduces the effective noise of an am- plifier driving its input. table 8 over- *rms *rms enob maximum first notch effective ?db sample noise noise (v ref = 5v) conversion rate frequency noise bw point (hz) ratio LTC2444/ ltc2445/ LTC2444/ ltc2445/ internal external internal external internal external internal external (osr) ltc2448 ltc2449 ltc2449 ltc2449 9mhz clock f o 9mhz clock f o 9mhz clock f o 9mhz clock f o 64 23 v23 v 17 17 3515.6 f o /2560 28125 f o /320 3148 f o /5710 1696 f o /5310 128 4.5 v 3.5 v 20.1 20 1757.8 f o /5120 14062.5 f o /640 1574 f o /2860 848 f o /10600 256 2.8 v2 v 20.8 21.3 878.9 f o /10240 7031.3 f o /1280 787 f o /1140 424 f o /21200 512 2 v 1.4 v 21.3 21.8 439.5 f o /20480 3515.6 f o /2560 394 f o /2280 212 f o /42500 1024 1.4 v1 v 21.8 22.4 219.7 f o /40960 1757.8 f o /5120 197 f o /4570 106 f o /84900 2048 1.1 v 750nv 22.1 22.9 109.9 f o /81920 878.9 f o /1020 98.4 f o /9140 53 f o /170000 4096 720nv 510nv 22.7 23.4 54.9 f o /163840 439.5 f o /2050 49.2 f o /18300 26.5 f o /340000 8192 530nv 375nv 23.2 24 27.5 f o /327680 219.7 f o /4100 24.6 f o /36600 13.2 f o /679000 16384 350nv 250nv 23.8 24.4 13.7 f o /655360 109.9 f o /8190 12.4 f o /73100 6.6 f o /1358000 32768 280nv 200nv 24.1 24.6 6.9 f o /1310720 54.9 f o /16380 6.2 f o /146300 3.3 f o /2717000 input bandwidth and frequency rejection the combined effect of the internal sinc 4 digital filter and the digital and analog autocalibration circuits determines the LTC2444/ltc2445/ltc2448/ltc2449 input band- width and rejection characteristics. the digital filters response can be adjusted by setting the oversample ratio (osr) through the spi interface or by supplying an exter- nal conversion clock to the f o pin. table 8 lists the properties of the LTC2444/ltc2445/ ltc2448/ltc2449 with various combinations of oversample ratio and clock frequency. understanding these properties is the key to fine tuning the characteris- tics of the LTC2444/ltc2445/ltc2448/ltc2449 to the application. maximum conversion rate the maximum conversion rate is the fastest possible rate at which conversions can be performed. applicatio s i for atio wu u u *adc noise increases by approximately 2 when osr is decreased by a factor of 2 for osr 32768 to osr 256. the adc noise at osr 128 and osr 64 include effects from int ernal modulator quantization noise. LTC2444/ltc2445/ ltc2448/ltc2449 26 sn2444589 2444589fs example: if an amplifier (e.g. lt1219) driving the input of an LTC2444/ltc2445/ltc2448/ltc2449 has wideband noise of 33nv/ hz, band-limited to 1.8mhz, the total noise entering the adc input is: 33nv/ hz ? 1.8mhz = 44.3 v. when the adc digitizes the input, its digital filter filters out the wideband noise from the input signal. the noise reduction depends on the oversample ratio which defines the effective bandwidth of the digital filter. at an oversample of 256, the noise bandwidth of the adc is 787hz which reduces the total amplifier noise to: 33nv/ hz ? 787hz = 0.93 v. the total noise is the rms sum of this noise with the 2 v noise of the adc at osr=256. (0.93 v) 2 + (2uv) 2 = 2.2 v. increasing the oversample ratio to 32768 reduces the noise bandwidth of the adc to 6.2hz which reduces the total amplifier noise to: 33nv/ hz ? 6.2hz = 82nv. the total noise is the rms sum of this noise with the 200nv noise of the adc at osr = 32768. (82nv) 2 + (200nv) 2 = 216nv. in this way, the digital filter with its variable oversampling ratio can greatly reduce the effects of external noise sources. applicatio s i for atio wu uu automatic offset calibration of external buffers/amplifiers the ltc2445/ltc2449 enable an external amplifier to be inserted between the multiplexer output and the adc input. this enables one external buffer/amplifier circuit to be shared between all 17 analog inputs (16 single-ended or 8 differential). the ltc2445/ltc2449 perform an inter- nal offset calibration every conversion cycle in order to remove the offset and drift of the adc. this calibration is performed through a combination of front end switching and digital processing. since the external amplifier is placed between the multiplexer and the adc, it is inside the correction loop. this results in automatic offset correction and offset drift removal of the external amplifier. the lt1368 is an excellent amplifier for this function. it has rail-to-rail inputs and outputs, and it operates on a single 5v supply. its open-loop gain is 1m and its input bias current is 10na. it also requires at least a 0.1 f load capacitor for compensation. it is this feature that sets it apart from other amplifiersthe load capacitor attenu- ates sampling glitches from the ltc2445/ltc2449 adcin terminals, allowing it to achieve full performance of the adc with high impedance at the multiplexer inputs. another benefit of the lt1368 is that it can be powered from supplies equal to or greater than that of the adc. this can allow the inputs to span the entire absolute maximum of gnd C 0.3v to v cc + 0.3v. using a positive supply of 7.5v to 10v and a negative supply of C2.5 to C5v gives the amplifier plenty of headroom over the ltc2445/ltc2449 input range. figure 16. simple external clock source 28 2 29 38 37 8 9 36 3 24448 f17 35 1,4,5,6,31,32,33 reference voltage 0.1v to v cc analog input C0.5v ref to 0.5v ref 3-wire spi interface 4.5v to 5.5v 30 v cc busy f o ref + sck ch0 ch1 sdo gnd cs ext ltc2448 ref C 1 f 0.1 f ltc1799 out div set gnd v + r set nc ? ? ? LTC2444/ltc2445/ ltc2448/ltc2449 27 sn2444589 2444589fs information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701) 5.00 0.10 (2 sides) note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 0.40 0.10 37 1 2 38 bottom viewexposed pad 5.15 0.10 (2 sides) 7.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0303 0.50 bsc 0.200 ref 0.200 ref 0.00 C 0.05 recommended solder pad layout 3.15 0.10 (2 sides) 0.18 0.18 0.23 0.435 0.00 C 0.05 0.75 0.05 0.70 0.05 0.50 bsc 5.20 0.05 (2 sides) 3.20 0.05 (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 6.10 0.05 (2 sides) 7.50 0.05 (2 sides) 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package LTC2444/ltc2445/ ltc2448/ltc2449 28 sn2444589 2444589fs linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/tp 0304 1k ? printed in usa related parts part number description comments lt1025 micropower thermocouple cold junction compensator 80 a supply current, 0.5 c initial accuracy ltc1043 dual precision instrumentation switched capacitor precise charge, balanced switching, low power building block ltc1050 precision chopper stabilized op amp no external components 5 v offset, 1.6 v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/ c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/ c max drift ltc1592 ultraprecise 16-bit softspan tm dac six programmable output ranges ltc1655 16-bit rail-to-rail micropower dac 1lsb dnl, 600 a, internal reference, so-8 ltc1799 resistor set sot-23 oscillator single resistor frequency set ltc2053 rail-to-rail instrumentation amplifier 10 v offset with 50nv/ c drift, 2.5 v p-p noise 0.01hz to 10hz ltc2412 2-channel, differential input, 24-bit, no latency ? adc 0.16ppm noise, 2ppm inl, 200 a ltc2415 1-channel, differential input, 24-bit, no latency ? adc 0.23ppm noise, 2ppm inl, 2x speed up ltc2414/ltc2418 4-/8-channel, differential input, 24-bit, no latency ? adc 0.2ppm noise, 2ppm inl, 200 a ltc2430/ltc2431 1-channel, differential input, 20-bit, no latency ? adc 0.56ppm noise, 3ppm inl, 200 a ltc2436-1 2-channel, differential input, 16-bit, no latency ? adc 800nv rms noise, 0.12lbs inl, 0.006lbs offset, 200 a ltc2440 1-channel, differential input, high speed/low noise, 2 v rms noise at 880hz, 200nv rms noise at 6.9hz, 24-bit, no latency ? adc 0.0005% inl, up to 3.5khz output rate softspan is a trademark of linear technology corporation. typical applicatio u C + C + 5v 0v 1/2 lt1368 1/2 lt1368 1 2 3 4 5 6 7 8 high speed ? adc mux muxoutn muxoutp adcinp adcinn 17 2444589 ta05 (external amplifiers) ltc2449 ch0-ch15/ com sdi sck sdo cs 0.22 f 0.22 f external buffers provide high impedance inputs and amplifier offsets are cancelled |
Price & Availability of LTC2444
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |